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After loading the last byte in the serial communications data register and receiving the TDRE flag, the user can clear TE. Transmission of the last byte will then be completed before the transmitter gives up control of the TxD pin. While the transmitter is active, the data direction register control for port D bit 1 is overridden and the line is forced to be an output. RE — Receive Enable When the receive enable bit is set, the receiver is enabled. When RE is clear, the receiver is disabled and all of the status bits associated with the receiver (RDRF, IDLE, OR, NF, and FE) are inhibited.
This prescaled output provides an input to a divider which is controlled by the SCR2-SCR0 bits. Table 5-1 First Prescaler Stage SCP1 SCP0 Internal Processor Clock Divided By 0 0 1 0 1 3 1 0 4 1 1 13 SCR2, SCR1, and SCR0 — SCI Baud Rate Selects These three bits select the baud rates for both the transmitter and the receiver. The prescaler output described above is further divided by the factors shown in Table 5-2. MC68HC11A8 TECHNICAL DATA SERIAL COMMUNICATIONS INTERFACE MOTOROLA 5-11 5 Table 5-2 Second Prescaler Stage 5 SCR2 SCR1 SCR0 Prescaler Output Divide By 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 RCKB — SCI Baud Rate Clock Check (Test) This bit is used during factory testing to enable the exclusive-OR of the receiver clock and transmitter clock to be driven out the TxD pin.
These registers can be relocated on 4K boundaries within the memory space, using the INIT register. Refer to Table 3-1 for a complete list of the registers. The registers and control bits are explained throughout this document. The INIT register is a special-purpose 8-bit register which may be used during initialization to change the default locations of RAM and control registers within the MCU memory map. It may be written to only once within the initial 64 E clock cycles after a reset and thereafter becomes a read-only register.